Traditionally, the contexts which benefit most from hardware co-processing have had identifiable computationally intensive tasks which could be isolated and mapped onto a custom designed ASIC (Application Specific Integrated Circuit). Whilst such custom ASIC's provide the desired application performance boost, they are expensive to develop and their tight coupling to a specific problem domain makes them inflexible. Their performance when applied to problem domains not specified in their original design is poor.
FPGAs, however, provide the hardware designer with the opportunity to combine increased performance through hardware co-processing, whilst at the same time maintaining a degree of design flexibility. This is possible by utilising the reconfigurable nature of FPGAs to tailor their behaviour to differing application specific domain at runtime.
The use of FPGA technology in the field of image processing has already been established. Convolution of greyscale images, for example, has been successfully implemented on the Splash 2 architecture, by researchers at Michigan State University, and Virginia Polytechnic Institiute and State University [see Proceedings of the IEEE Conference, FCCM'95: Convolution on Splash 2, and IEEE Computer Feb'95: Real Time Image Processing on a Custom Computing Platform].
reACT is a project aimed at investigating the implementation feasibility of image processing algorithms on reconfigurable hardware and modelled to a maximal extent using behavioural VHDL.
The algorithms tagged for investigation at this stage are highlighted below. The final engine will hopefully support the following image processing operations over 24bit RGB images.