Available Papers on Asynchrony :

SIS : A System for Sequential Circuit Synthesis, University of California - Berkeley.

Synchronous clocked and self-timed pipeline configurations, Siemens.

Self-Timed Architecture of a Reduced Instruction Set Computer, Israel Institute of Technology.

Tutorial - The Systematic Design of Asynchronous Circuits, ICCA 95.

The Design of a Fast Asynchronous Microprocessor, University of Adelaide.

Performance Issues on Micropipelines, Oregon State University.

Parallel Structures for Asynchonous Microprocessors, University of Machester.

Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits, Stanford University.

Fred: An Architecture for a Self-Timed Decoupled Computer, University of Utah.

Practical Verification and Synthesis of Low Latency Asynchronous Systems, University of Calgary.

Unifying Synchronous/Asynchronous State Machine Synthesis, Stanford University.

Available papers on Computer Architecture :

Limits of Control Flow on Parallelism, Stanford University.

Extraction of Massive Instruction Level Parallelism, University of Rhode Island.

The Pentium Processor's Microarchitecture, Intel.

Instruction Fetching Mechanisms for Superscalar Processors, University of California.

Register Connection : A New Approach to Adding Registers into Instruction Set Architectures,

A Scalable Register File Architecture for Dynamically Scheduled Processors, University of California.

New Paradigms for Instruction-Level-Parallelism, University of Wisconsin-Madison

Non-Consistent Dual Register Files to Reduce Register Pressure, University of Catalunya.

Performance Analysis of a Superscalar Architecture, University of California.

Using Sacks to Organise Registers in VLIW Machines, University of Catalunya.

Compressed Reduced Instruction Set COmputing (CRISCO), Galicia & Warner.

Out-of-Order Execution of Interruptable Codes, INRIA.

The Effectiveness of Decoupling ACRI, Universities of Manchester, Edinburgh.

General Purpose Optimistic Parallel Computing, University of Exeter.

The Architecture of an Optimistic CPU: The WarpEngine, Universities of Waikato, Calgary.

The Microarchitecture of Superscalar Processors, University of Wisconsin-Madison.

Multiscalar Processors, University of Wisconsin-Madison.

Performance of the Decoupled ACRI-1 Architecture: the Perfect Club, Universities of Edinburgh, St. Andrews, ACRI.

The Performance Impact of Incomplete Bypassing in Processor Architectures, Princeton University.

Advanced Performance Features of the 64-bit PA-8000, Hewlett-Packard.

On the Limits of Program Parallelism and its Smoothability, McGill University.

Performance Fctors for Superscalar Processors, Stanford University.

NIW: A Simple Superscalar Architecture, University of Western Ontario.

Compiling for Efficient Memory Utilisation, University of Virginia.

Design and Evaluation of Dynamic Access Ordering Hardware, University of Virginia.

Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading, University of Washington, Digital.

Instruction-Processing Optimisation Techniques for VLSI Microprocessors, University of Texas.