Institute for Computing Systems Architecture

Division of Informatics, University of Edinburgh

EVALUATION OF MULTIPROCESSOR INTERCONNECTION NETWORKS

The SimJava Applets

The Basic MIN Testbed

This simulation shows four CPUs connected to four memory modules via a multistage switching network. The inputs to the network are at the top - the first four ports are inputs from the CPUs and the next four ports are inputs from the memory modules. Along the bottom (output) of the multistage network, again the first four ports go back to the CPUs and the next four ports go to the memories.

Running the simulation (by pressing the Run button) causes the CPUs to generate their workload. For this simulation model, each CPU does a number of memory accesses to the first memory module. The activity of the network switches can be seen when their state changes from idle () to busy (). Similarly the CPUs state can be idle (), reading () or waiting for a read request to return (). The memory is either idle () or reading ().

Toggling the show trace button switches the animation on and off (with the animation switched off, the simulation runs faster, but since this model has no results display, there is nothing to see on screen). The show messages button usually selects whether or not to animate individual messages down links, but this feature is not enabled in this model. The speed slider selects the time in milliseconds between animation updates. layout resets the display, run starts the simulation, pause pauses it and stop stops it.

The purpose of this model is to demonstrate the basic model animation facilities provided by the testbed. In this case the visual feedback shows that only the first MEM is accessed, and also shows the dynamic pattern of accesses through the network.

The applet's source code.

Fred Howell - fwh@dcs.ed.ac.uk