Institute for Computing Systems Architecture
Division of Informatics, University of Edinburgh
EVALUATION OF MULTIPROCESSOR INTERCONNECTION NETWORKS
The SimJava Applets
Testbed with timing diagram.
This example shows how timing diagrams can be generated on the
fly as simulations run. The timing diagram can be scrolled
and zoomed once the simulation has finished; it is implemented
as a JavaBean software component. Initially the timing diagram display
is empty; as the simulation proceeds, the state changes are displayed
on the diagram as different coloured
bars (with the meaning provided by the key below).
The applet's source code.
Fred Howell -
fwh@dcs.ed.ac.uk