Michael O'Boyle


Professor, FBCS
PhD, University of Manchester, 1992
Email: mob at inf dot ed dot ac dot uk
Phone: 0131 650 5117

ACM ASPLOS 2021 Distinguished paper award Neural Architecture Search as Program Transformation Exploration
IEEE HPCA 2021 Best paper award Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design
ACM GPCE 2020 Best paper award Modeling black-box components with probabilistic synthesis

I am interested in recruiting students in any of the areas covered by my research interest or current projects. I also open minded - if you have a great idea you would like to pursue - get in touch!

Director of ARM Research Centre of Excellence
EPSRC Established Career Research Fellow
Director of EPSRC CDT in Pervasive Parallelism

Research Interests

The primary research questions I am interested in are: (i) how can compiler technology best exploit the potential of high performance heterogeneous architectures (ii) how can we best design high performance heterogeneous to meet emerging applications.

My research interests include:

  • Heterogeneous Code discovery and Optimisation. I am interested in how we can use diverse techniques including constraint analysis, program synthesis and machine learning to discover code patterns that match heterogeneous hardware and automatically tune them.
  • Neural Machine Translation and Neural Synthesis I am interested in how transformer based models can aid translation from one programming language to another and how program behaviour can be exploited to drive automatic synthesis of high level code.
  • Deep Neural Network system stack. I currently investigate how to optimise deep learning training and inference based on real world device constraints. I am interested in a cross-stack approach incorporating Bayesian Optimisation at the model layer and a device specific optimisations at the hardware layer to unify neural architecture search and program transformation.
  • Software Defined Hardware. I currently investigate how to map languages such as Python to flexible hardware (e.g. coarse-grain reconfigurable architectures). I am interested in both how software may be adapted to fit hardware and hardware reshaped for software.
  • Auto-parallelising compilers. I am currently investigating the use of dynamic, probabilistic analysis in conjunction with machine learning to develop a new approach that gives future proof scalable code for multi-cores.
  • GPGPU multi-core platforms. I am interested in how we can use smart compiler analysis and adaptation to exploit the potential of such architectures for compute and graphics workloads.
  • Machine learning based optimisation. I'm interested in how predictive modelling and feature generation can be used to automate the design of compilers
  • Compiler/Architecure co-design space exploration. We are investigating the use of predictive models to predict the best compiler optimisations for any architecture
  • Very High level programming languages. I am interested in how languages such as Matlab, which provide great expressive power may be implemented on multi-cores

    • Current projects

  • Redesigning compilers for heteregeneous hardware in my 5 year EPSRC fellowship
  • Optimising Deep Learning on Embedded devices in the Bonseyes project
  • Software Defined Hardware in the Transmuter project
  • Discovering heterogeneity in code in the Discovery project
  • Computer systems for Real time vision and robotics in the Pamela project

    • I am a member of the Compiler and Architecture Design Group.
    Steering Committee and Partner of HiPEAC Network of Excellence

    Papers from 1997 onwards can be found on the CArD publications page. Earlier papers 1992-1996 can be found here

    References also available from DBLP and Google Scholar

    A short CV

    Students and PostDocs

  • Jordi Armengol-Estape Compilation as Neural Machine Translation
  • Celeste Hollenbeck Machine Learning and programming languages
  • Jackson Woodruff Heterogeneous Accelerators
  • Bruce Collie Program Synthesis for heterogeneous hardware
  • Jack Turner Cross-stack DNN optimisation
  • Lewis Crawford ARM Centre of Excellence. Graphics compilation
  • Kuba Kaszyk Transmuter

    • Former Students and PostDocs

  • Jiawen Sun Transmuter. Now at HiSilicon
  • Magnus Morton Transmuter. Post-doc ICSA
  • Valentin Radu Bonseyes. Now Lecturer U Sheffield
  • Lu Li Transmuter. Now at Zenseact
  • Philip Ginsbach Heterogeneous code discovery. Now at Microsoft.
  • Jose Cano Reyes Bonseyes. Now lecturer at Glasgow
  • Yuan Wen Pamela. Heterogeneous task scheduling. Now at Trinity College, Dublin
  • Bruno Bodin Pamela. Parallel compilation and computer vision. Now at NUS Singapore
  • Govind Sreekar Shenoy Pamela. Hardware design space exploration and computer vision. Now at Intel
  • Murai Emani . Machine learning based adaptive scheduling. Now at Argonne National Labs
  • Kiran Chandramohan . Compiling for heterogeneous multicores. Now at ARM
  • Chris Margiolas . Runtime systems for heterogeneous platforms. Now at Intel Research
  • Alberto Magni ARM Centre of Excellence. OpenCL compilation. Now at MSR Cambridge
  • Erik Tomusk ARM Centre of Excellence. Design space exploration. Now at CodePlay.
  • Dominik Grewe Now at Deep Mind London.
  • Zheng Wang Now associate professor at U. Leeds
  • Christophe Dubach Royal Academy of Engineering / EPSRC Research Fellow . Now Assoc. Professor at McGill University
  • Hugh Leather Royal Academy of Engineering / EPSRC Research Fellow. Now reader at U.Edinburgh
  • John Thomson Now lecturer at University St Andrews.
  • John Cavazos COLO. Assoc.professor at University of Delaware. Sadly no longer with us.
  • Tim Jones Royal Academy of Engineering / EPSRC Research Fellow. Now Reader at U. Cambridge
  • Bjoern Franke Now Professor at U.Edinburgh.
  • Tom Ashby Now at IMEC.
  • Shun Long Now Associate Professor Jinan University
  • Grigori Fursin Now at dividiti.

    • Prospective PhD Students

    I am interested in supervising PhD students in any of the above research areas. For further details, please use the contact information at the top of this page