This module runs in term 1, with lectures on Mondays at 11am, in JCMB lecture theatre B, and on Thursdays at 11am, in Chemistry T250. Hardware labs take place 2-5pm on Wednesday, Thursday and Friday afternoons, starting in week 2. Lab afternoons and partners will be allocated during week 1.

• Module overview (also in postscript or pdf).

• The lecture handouts contain many hand-drawn diagrams, so are not available online. Copies may be obtained from the ITO. Handouts given out so far are as follows:
  • on Oct 12th: Module overview. Hardware lab manual. Logic Level Design (pages 1 - 17).
  • on Oct 19th: Combinational Logic Implementation (pages 18 - 28).
  • on Oct 23rd: Sequential Logic Design (pages 29 - 43). Lab manual for practicals 2b, 3a and 3b. Example circuit diagram for lab.
  • on Oct 30th: Design of Sequential Logic Circuits (pages 44 - 58).
  • on Nov 9th: Processor Design (pages 60 - 64) (there is no page 59).
  • on Nov 13th: Instruction Set Processor Design (pages 65 - 71).
  • on Nov 16th: Design of more complex ISPs (pages 72 - 78).
  • on Nov 20th: Lab manual for practical 4.
  • on Nov 23rd: ALU design (pages 79 - 96).
  • on Dec 4th: Memory design (pages 97 - 104).
  • on Dec 7th: Interconnection of CPU and memory (pages 105 - 119. The last handout).

• Lecture log

• Hardware lab manual (now including pracs 2b, 3a and 3b), without diagrams I'm afraid! The ITO has printed copies available.

• Past Examination Papers
  • June 1999

• Lab afternoons and partners

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Tim Hopkins, tmh@dcs.ed.ac.uk, JCMB room 2616, 0131 650 5153