Rob Payne: PhD Thesis
Self-Timed Field Programmable Gate Array Architectures
Abstract:
Dynamic hardware systems exploit the in-system reconfigurability of Field
Programmable Gate Arrays (FPGAs), but are currently limited by the
delay properties of synchronous FPGA architectures. Synchronous
circuits are difficult to manipulate dynamically, since this alters
their internal delays. The speed-independent properties of self-timed
circuits overcome this problem, thus allowing the full benefits of
dynamic reconfiguration to be exploited. The general properties of
self-timed systems, such as modularity, low power and data dependent
delays also provide benefits to less dynamic FPGA systems as well.
This thesis introduces a model for self-timed FPGA architectures
called STACC (Self-Timed Array of Configurable Cells). STACC
architectures replace the global clock of an FPGA with an array of
timing cells that provide local self-timed control to a region of
logic blocks. STACC differs from previous self-timed FPGA
architectures in that it does not disrupt the structure of the logic
blocks.
The STACC model is used to produce a self-timed version of the Xilinx
XC6200 FPGA. Example circuits for the self-timed XC6200 demonstrate
the benefits of self-timing for implementing dynamic hardware systems.
Evaluation of the architecture shows that the implementation overhead
of the timing array is reasonable, and that the self-timed XC6200 has
the potential to out-perform the synchronous XC6200 through use of
data dependent delays.
Thesis Contents:
Thesis Structure
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Part I: Introduction
- Chapter 1 gives a general introduction to the
thesis and how it is structured.
- Chapter 2 covers background material on FPGAs. A
key part of this chapter is the discussion of dynamic hardware systems,
virtual hardware, and run-time parameterised circuits.
- Chapter 3 introduces self-timed systems and
includes a detailed discussion of bundled-data systems.
- Chapter 4 is central to the rest of the
thesis. It considers the potential benefits and drawbacks of
self-timing for FPGA systems in general, and dynamic hardware in
particular. The chapter also reviews the current research on
self-timed circuits using synchronous FPGAs and proposed self-timed
FPGA architectures.
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Part II: STACC
- Chapter 5 introduces a model for self-timed
FPGA architectures: STACC (Self-Timed Array of
Configurable Cells). The STACC model
involves replacing the global clock in a synchronous FPGA with an
array of timing cells that provide local clock signals.
STACC Structure
- Chapter 6 introduces several new self-timed
elements, such as the Q-Merge/Select pair and the reconfigurable
C-Muller gate, which are used as building blocks for the timing array.
- Chapter 7 describes in
detail the design of timing cells for STACC. The timing cell is
developed from a basic reconfigurable C-Muller gate into a timing cell
capable of selective communication and arbitration.
- Chapter 8 concerns routing structures for handshaking
signals in the STACC timing array. These structures are based on
another development of the reconfigurable C-Muller
gate: the handshaking crossbar.
Part III: A Self-Timed XC6200
Self-Timed Xilinx XC6200 Cross-Section
- Chapter 9 introduces the current XC6200
architecture, concentrating on the features useful for dynamic
hardware, and then presents the design of a self-timed XC6200 using
the STACC model.
- Chapter 10 contains a case study
of the use of the self-timed XC6200 for implementing dynamic hardware
systems. The example circuits are run-time parameterised circuits for
finite field operations with application to Reed-Solomon
error correction.
- Chapter 11 compares
the self-timed XC6200 relative to the synchronous XC6200, considering
its delay performance and the implementation overhead of the timing
array.
Part IV: Conclusions
- Chapter 12 summarises the
main results of the work. The chapter ends with a discussion of
possible directions for future research.
Downloading the thesis
Rob Payne
Last modified: Thu Sep 4 11:53:35 BST 1997