Self-Timed FPGAs

Below, groups which have done work on self-timed FPGA systems are listed. They are classified into two sets: those groups involved in research on new self-timed FPGA architectures and those involved in the implementation of self-timed circuits on current synchronously-oriented commercial devices.

My work falls into the first category, since I believe that to get the most out of self-timed FPGA systems needs new FPGA architectures tailored towards the implementation of self-timed circuits (see [2]). However, the works on implementing self-timed circuits on current devices shows that implementation on present devices is possible. But, these works also highlight the difficulties and limitations of current synchronously-oriented FPGAs for implementing self-timed systems.

At the end of this page, details of the self-timed FPGA system bibliography is given which lists the various papers published by the groups listed.

The STACC Architecture

STACC is currently my favourite acronym for my work. (STACC = Self-Timed Array of Configurable Cells). My proposed architecture is specifically targeted at implementing bundled-data systems. The architecture has two types of cell: timing cells that provide timing signals to a larger number of data cells. For the gory details see [2].

Animations

Below are some gzipped postscript files of some VHDL simulations of the STACC architecture to give you a feel for how it works. You should be able to view the sequences frame by frame using ghostview, though you can't randomnly access pages at present (the technical reason for this is that I use copypage rather showpage in the postscript to save redrawing the page every time). By running the postscript through this short Perl script , and piping the output to ghostview with perl animate.perl adder.ps | ghostview - then you can animate the sequences and save all that wear and tear on the space bar.

There's no explanation of the examples at present, however, a document that explains the examples is being prepared.

• Pipeline Examples

• Branching Example

• Toggling and DeToggling Example

• Arbitration Example

Other Self-Timed FPGAs Architectures

• Washington, the MONTAGE architecture: Unfortunately these guys thought up Asynchronous FPGAs first. Luckily their ideas are substantially different. They have chosen to target the implementation of all forms of asynchronous circuits and just for good measure, synchronous ones as well. See [4][3].

• U.C.Davis, the PGA-STC architecture : The PGA-STC is a new architecture which is loosely modelled on the Xilinx range of FPGAs. It is closer to my own work, in that it is targetted at bundled-data systems and hence has dedicated delay elements. A paper by Maheswaran and Akella is in the pipeline (or should that be micropipeline) at present.

Self-Timed Circuits on Current FPGAs

• Utah: Eric Brunvand's work on implementing micropipelines on Actel parts [7], including the NSR [5] and Windchime [6] processors.

• Strathclyde: Asynchronous circuits implemented on a CAL-based transformable system, the SPACE machine [13].

• Syracuse: Implementations of micro-pipelined FIFOs on Algotronix CAL devices, together with a comparison with a dedicated silicon implementation [12].

• U.C.Davis: Their work has concentrated on implementing Micropipelines on Xilinx parts. Available are various assorted papers on the design of a Xilinx self-timed cell library [9][8], a self-timed multiplier [10].

• Manitoba: More implementations of micro-pipelines on Xilinx devices, including a paper on implementing a self-timed multiplier [11].

• Sussex: A scheme for evolvable hardware using asynchronous circuits in FPGAs [14] from Adrian Thompson (who happens to be a fellow UMIST Micro-electronic Systems graduate).

Self-Timed FPGA System Bibliography

The self-timed FPGA system Bibliography is available here. It's a pretty short bibliography file at present since not much work has been done in the area. To add your own or someone else's contribution to the bibliography then send mail to rep@dcs.ed.ac.uk. To view the WWW version, which includes links to the papers if they are WWW accessable, go to section 4.