NEW: Animations of the STACC
architecture are now available.
In the last decade, FPGAs have emerged as the dominant form of programmable logic. An important difference of FPGAs from previous programmable logics is that many FPGAs may be reconfigured in-system. This ability of FPGAs to act as `soft-hardware' is being utilised in many new custom computing systems, often known as transformable systems.
During the same period as the emergence of FPGAs, there has been renewed interest from the academic community in self-timed design. Self-timed systems offer many advantages over their synchronous counterparts in terms of performance, robustness, modularity and power consumption.
The application of a self-timed methodology to transformable systems has many potential benefits. Principal amongst them is that the modularity and robustness of self-timed circuits would allow flexible and fast mappings to the reconfigurable hardware. (see [2] for a full discussion of the benefits). However, only a small body of work currently exists concerning the implementation of self-timed systems on FPGAs.
The aim of this page is to collect together the current small body of work on self-timed FPGA systems. Links are provided to groups involved in the field plus a bibliography of the current works. Links to general information on FPGAs and asynchronous/self-timed design are also included.
If you have any comments on this page or know of any work on self-timed FPGA systems that is not included below then please mail me at rep@dcs.ed.ac.uk.