The platform that was given to our group was the Hitachi SH2DSP. A DSP (Digital Signal Processor) is a specialised processor for performing complex calculations faster than a `normal' processor. This allows the calculation blocks of the behaviours to be mapped to an appropriate processor depending of whether the block contains simple or complex calculations.
The features of the SH2DSP (paraphrased from the SH1, SH2, SH-DSP Programmer's Reference):
The SH-2 has a RISC-type instruction set. Basic instructions are executed in one clock cycle, which dramatically improves instruction execution speed. The CPU also has an internal 32-bit architecture for enhanced data processing ability. Table 1 lists the SH-2 CPU features.
Architecture |
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General-register machine |
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Instruction Set |
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Instruction execution time |
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Address space |
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On-Chip multiplier |
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Pipeline |
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Processing states |
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Power-down states |
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The SH-DSP is a 32-bit microcontroller based on the Hitachi SuperH RISC engine (abbreviated below as "SuperH") and incorporating the signal processing performance of a general-use digital signal processor (DSP). The SuperH already supported some DSP type instructions, such as multiply and accumulate. In the SH-DSP, the DSP functions have been enhanced, and full DSP data bus have been implemented. The SH-DSP is backward compatible at the object code level with the SH-1 and SH-2 CPUs.
The SuperH only has 16-bit instructions. The SH-DSP basically has the same 16-bit instructions, but it also has additional 32-bit DSP instructions that it uses for parallel processing of DSP type instructions. The SuperH uses a standard Neumann architecture, but the SH-DSP has the DSP data bus of the expanded Harvard architecture.
Table 2 lists the added features of the SH-DSP.
DSP Unit |
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DSP registers |
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DSP data bus |
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Parallel processing |
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Address operator |
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DSP data addressing modes |
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Repeat control |
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Instruction set |
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Pipeline |
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The SH2DSP processor is a variable-speed processor setup. This means that the bus and clock speeds are variable within limits. To preserve comparibility of results I have used the following setup for all tests:
These speeds are basically just the fastest that the processors are spec'cd to go.
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