Description of the Platform

The platform that was given to our group was the Hitachi SH2DSP. A DSP (Digital Signal Processor) is a specialised processor for performing complex calculations faster than a `normal' processor. This allows the calculation blocks of the behaviours to be mapped to an appropriate processor depending of whether the block contains simple or complex calculations.

The features of the SH2DSP (paraphrased from the SH1, SH2, SH-DSP Programmer's Reference):


SH-2 Features

The SH-2 has a RISC-type instruction set. Basic instructions are executed in one clock cycle, which dramatically improves instruction execution speed. The CPU also has an internal 32-bit architecture for enhanced data processing ability. Table 1 lists the SH-2 CPU features.

Item
Feature
Architecture
  • Original Hitachi Architecture
  • 32-bit internal data bus
General-register machine
  • Sixteen 32-bit general registers
  • Three 32-bit control registers
  • Four 32-bit system registers
Instruction Set
  • Instruction length: 16-bit fixed length for improved code efficiency
  • Load-store architecture (basic arithmetic and logic operations are executed between registers)
  • Delayed branch system used for reduced pipeline disruption
  • Instruction set optimized for C language
Instruction execution time
  • One instruction/cycle for basic instructions
Address space
  • Architecture makes 4 Gbytes available
On-Chip multiplier
  • Multiplication operation executed in 1 to 2 cycles (16 bits x 16 bits -> 32 bits) or 2 to 4 cycles (32 bits x 32 bits -> 64 bits), and multiplication/accumulation operation executed in 3/(2)*cycles (16 bits x 16 bits + 64 bits -> 64 bits) or 3/(2 to 4)*cycles (32 bits x 32 bits + 64 bits + 64 bits -> 64 bits)
Pipeline
  • Five-stage pipeline
Processing states
  • Reset state
  • Exception processing state
  • Program execution state
  • Power-down state
  • Bus release state
Power-down states
  • Sleep mode
  • Standby mode
Table 1 - SH2 CPU Features

SH-DSP Features

The SH-DSP is a 32-bit microcontroller based on the Hitachi SuperH RISC engine (abbreviated below as "SuperH") and incorporating the signal processing performance of a general-use digital signal processor (DSP). The SuperH already supported some DSP type instructions, such as multiply and accumulate. In the SH-DSP, the DSP functions have been enhanced, and full DSP data bus have been implemented. The SH-DSP is backward compatible at the object code level with the SH-1 and SH-2 CPUs.

The SuperH only has 16-bit instructions. The SH-DSP basically has the same 16-bit instructions, but it also has additional 32-bit DSP instructions that it uses for parallel processing of DSP type instructions. The SuperH uses a standard Neumann architecture, but the SH-DSP has the DSP data bus of the expanded Harvard architecture.

Table 2 lists the added features of the SH-DSP.

Feature
Description
DSP Unit
  • 1 cycle multiplier
  • 16 bits x 16 bits -> 32 bits (fixed decimal point)
  • Arithmetic logic unit (ALU)
  • Barrel shifter
  • DSP registers
  • MSB detection
DSP registers
  • Two 40-bit data registers
  • Six 32-bit data registers
  • DSP status register (DSR)
  • Modulo register (MOD, 32 bits) added to control registers
  • Repeat counter (RC) added status registers (SR)
  • Repeat start register (RS) and repeat end register (RE) added to control registers
DSP data bus
  • Expanded Harvard architecture
  • Simultaneous access of two data bus and one instruction bus
Parallel processing
  • Maximum of four parallel processes (ALU operation, multiplication, and two loads or stores)
Address operator
  • Two address operators
  • Address operations for accessing two memories
DSP data addressing modes
  • Increment, decrement and index
  • Increment, decrement and index can have modulo addressing or not
Repeat control
  • Zero-overhead repeat control (loop)
Instruction set
  • 16 or 32 bits
    • 16 bits (for load or store only)
    • 32 bits (including for ALU operations and multiplication)
  • SuperH microprocessor instructions added for accessing DSP registers
Pipeline
  • Five-stage pipeline
  • Fifth stage is both the WB stage and the DSP stage
Table 2 - Features of SH-DSP Series Microprocessor CPUs

The SH2DSP processor is a variable-speed processor setup. This means that the bus and clock speeds are variable within limits. To preserve comparibility of results I have used the following setup for all tests:

These speeds are basically just the fastest that the processors are spec'cd to go.

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