Micronet: An operational model for System Level Intergration


Micronet[1][2] is a network of entities which operate concurrently and communicate asynchronously. The entities can be one of the following types: computational elements (usually digital), sensors (Analogue/Mixed Signal) or actuators (MEMS).

Micronets present a uniform model at the different levels of abstraction, i.e. a fractal model of system design: network of sub-systems, each sub-system, in turn, is a network of functional units, down to network of transistors

Control is layered: threads, compounds, instructions, microoperations, datapath control, handshaking protocol, signal transitions.

Micronets distribute control locally - behaviour can be decomposed to run on architectural clusters tailored with the optimal mix of computational elements.

Micronets make a clean separation between computation and communication, and, between behaviour and timing, which leads to a compositional design style.

The entities can be either clocked or self-timed; implementations using the latter exhibit lower power consumption[11] and better EMI characteristics.

Micronet-based Asynchronous Processor (MAP) have been designed for scalar[1], supers calar[5][6], VLIW[4] and multithreaded architectures[7] together with their parallelising compilers[12].

Behaviour-Achitecture Co-design: It is our belief that future Integration Platforms will be overwhelmingly programmable, consisting of soft-programmable forms - as instruction set architectures, and hard-programmable forms - realised as field programmable logic. The Integration Platform is composed of networks (micronets) of heterogeneous computational entities that operate in a multi-threaded fashion. The Application is composed of behavioural blocks - some pre-defined such as communication protocols; others, are more specific to the application. The first step in the co-design is to recognise concurrent operations and optimise communications at different levels and map them to the platform. The second step is to explore the trade-off between programmability (both soft and hard), and performance (in terms of speed and energy consumption) of the applications executing on the Integration Platforms.

Power point slides of a recent lecture (Feb. 2002)

Selected Publications

[1] Arvind, D. K. and Rebello, V . E. F. 1994. ``Instruction-level Parallelism in Asynchronous Processor Architectures'' Proc. of the Third International Workshop of Algorithms and Parallel {VLSI} Architectures, Elsevier, Leuven, Belgium, August 1994.

[2] Arvind, D. K., Mullins, R. D. and Rebello, V .E. F. 1995. ``Micronets: A model for decentralising control in asynchronous processor architectures'', In Proc. Int. Workshop on Asynchronous Design Methodologies, pp 190-99, IEEE Press, London, England, May 1995.

[3] Arvind, D. K. and Rebello, V. E. F. 1996. Static Scheduling of Instructions in Micronet-based Asynchronous Processors, Proc. of the 2nd Int. Symp. on Advanced Research on Asynchronous Circuits and Systems (ASYNC'96), pp 80-91, Aizu Wakamatsu City, Japan, March 1996

[4] Arvind, D. K. and Sotelo-Salazar, S. 1997. ``Scheduling instructions with uncertain latencies in asynchronous architectures'', In Proc. EUROPAR'97, Springer-Verlag, Passau, Germany, Aug, 1997.

[5] Arvind, D. K. and Mullins, R. D. 1999. ``A fully asynch ronous superscalar architecture'', In Proc. PACT'99 - Workshop on Parallel Architectures and Compilation Techniques, IEEE Press, Newport Beach CA, USA, Oct. 1999.

[6] Arvind, D. K. and Mullins, R. D. 2000. ``Instruction Issue and Data Forwarding Mechanisms for Asynchronous Superscalar Processors'', In Proc. Workshop on Complexity-Effective Design at ISCA2000, Vancouver, Canada, June 2000.

[7] Arvind, D. K. and Rangaswami, R. 1999, ``Asynchronous Multithreaded Processor Cores for System Level Integration'', In Proc. IP'99, November 1999, Edinburgh, pp 105-10, Miller Freeman.

[9] Arvind, D. K. and Lewis, T. 1998. Dependency Analysis of Recursive Data Structures using Automatic Groups, Languages and Compilers for Parallel Computers, LCPC'98, Chapel Hill NC, USA, 7-9 Aug 1998, Springer-Verlag.

[10] Arvind, D. K. and Lewis, T. 2000. Safe Approximation for Data Dependencies in Pointer-based Structures, Accepted for presentation at the 13th International Workshop on Languages and Compilers for High-Performance Computing, Yorktown Heights, NY, USA, 10-12 Aug 2000, Springer-Verlag.

[11] Arvind, D. K. and Hildingsson, K. 2000. Power Tradeoffs in Asynchronous Interfaces, In Proc. of the Workshop on Asynchronous Intefaces, Delft, The Netherlands, 19-20 July 2000.

[12] Arvind, D. K., Hossell, J., Koppe, A. and Rangaswami, R. 2001. Java Compilation for Multithreaded Architectures, In Proc. of the 9th Workshop on Compilers for Parallel Computers, Edinbrugh, Scotland, 27-29 June 2001.

[13] Arvind, D. K., Hossell, J., Koppe, A., Lewis, T., Rangaswami, R., Schneiders, J., Stanley, S., and Zhong. S. 2001. A Design Framework for Asynchronous Multithreaded Architectures, In Proc. 10th UK Asynchronous Forum, Edinburgh, Scotland, 2-3 July 2001.

[14] Arvind, D. K. and Schneiders, J. 2001. Area Virtual Time, In Proc. 5th IEEE International Workshop on Distributed Simulation and Real Time Applications, Cincinnati, USA, 13-15 August 2001.

[14] Arvind, D. K. and Bainbridge, C. 2001. Micronet-based CISC Architectures, In Proc. 11th UK Asynchronous Forum, Cambridge, England, 17-18 December 2001.

[14] Arvind, D. K. and Zhong, S. 2002. Hard- and Soft-Programmable, Multithreaded Micronet Architectures, In Proc. 12th UK Asynchronous Forum, London,England, 17-18 June 2002.

DK Arvind.