CS3 Computer Architecture Assignment 1998
Part II - ``Locality and Cache Design''

Issue date: Tuesday 10th February

Due date: Friday 13th March

The purpose of this second part of the coursework is to determine the design parameters for the data cache of a hypothetical new machine. Following the principles of quantitative design, you must measure and report the effectiveness of your cache proposal. Your design is constrained by a small set of predefined parameters and a range of allowable costs. These parameters, and the mechanism by which you are to compute the cost of your design, are both given in this handout.

You may assume that the machine under consideration has separate instruction and data caches, and that data and instructions are brought into these caches from main memory. All predefined parameters of the cache and memory systems are given in table 1 below.

 

 

CPU clock frequency 166 MHz

Max. cache hit time 5.8 nS

Main memory latency 20 cycles

Main memory bandwidth 2 32-bit words per cycle

Bus width 2 32-bit words

Bus transfer time 2 cycles

$$2000\pm 20\%$$ Budget ECU

The parameters that you must determine for the data cache are given in table 2 below. This uses some acronyms which are detailed in table 3. For a more complete interpretation of the various cache policies mentioned below you should refer to the course text book (Hennessy & Patterson) as well as the man page for dinero.

Your proposed cache design must have access and cycle times less than or equal to the maximum cache hit time shown in table 1. Cache timings can be checked using the cacti program which is explained below.

 

 

Block size - bytes

Associativity - (none)

Total capacity - bytes

Write policy - CB or WT?

Write allocation policy - WA or NWA?

Replacement algorithm - RND, LRU or FIFO?

 

 

CB Copy-Back write policy

WT Write-Through write policy

RND RaNDom replacement policy

LRU Least Recently Used replacement policy

FIFO First-In-First-Out replacement policy