Publications
Thesis
Conference
Journal
Self-Timed Field Programmable Gate Array Architectures
Reference
R.E.Payne. Self-Timed Field Programmable Gate
Array Architectures Ph.D. Thesis, University of Edinburgh, 1997.
Abstract
Dynamic hardware systems exploit the in-system reconfigurability of Field
Programmable Gate Arrays (FPGAs), but are currently limited by the
delay properties of synchronous FPGA architectures. Synchronous
circuits are difficult to manipulate dynamically, since this alters
their internal delays. The speed-independent properties of self-timed
circuits overcome this problem, thus allowing the full benefits of
dynamic reconfiguration to be exploited. The general properties of
self-timed systems, such as modularity, low power and data dependent
delays also provide benefits to less dynamic FPGA systems as well.
This thesis introduces a model for self-timed FPGA architectures
called STACC (Self-Timed Array of Configurable Cells). STACC
architectures replace the global clock of an FPGA with an array of
timing cells that provide local self-timed control to a region of
logic blocks. STACC differs from previous self-timed FPGA
architectures in that it does not disrupt the structure of the logic
blocks.
The STACC model is used to produce a self-timed version of the Xilinx
XC6200 FPGA. Example circuits for the self-timed XC6200 demonstrate
the benefits of self-timing for implementing dynamic hardware systems.
Evaluation of the architecture shows that the implementation overhead
of the timing array is reasonable, and that the self-timed XC6200 has
the potential to out-perform the synchronous XC6200 through use of
data dependent delays.
Availability
- See the Thesis Home Page for
more details about the thesis and to download a copy.
Self-Timed FPGA Systems
Reference
R.E.Payne Self-Timed FPGA Systems
Proceedings of the 5th International Workshop on Field
Programmable Logic and Applications, LNCS 975, September 1995.
Abstract
Recently, there has been a renewal of interest in self-timed systems, due
to their modularity, robustness, low-power consumption and average-case
performance. Additionally, this paper argues that there are
specific benefits to adopting self-timed design for FPGAs. The
mapping problems of placement, routing and partitioning are
simplified by not having a global clock constraint to meet, so more
mappings are available for mapping algorithms to choose from. Hence,
there is greater potential for algorithms to improve utilisation and
performance of a design, or instead, to increase design turn-around by
taking less time to produce a mapping. Furthermore, the ability to
perform mappings quickly enables new FPGA applications where the
mapping to the FPGA is done on-the-fly. However, currently available FPGAs
provide no support for self-timed design. The latter half of the
paper describes the STACC architecture, an FPGA architecture
targeted at the implementation of self-timed bundled-data systems.
Availability
Self-Timed Reconfigurable Elements
Reference
R.E.Payne Self-Timed Reconfigurable
Elements Proceedings of the First U.K. Asynchronous Forum, December 1996.
Abstract
The presentation outlines my research into self-timed FPGA
architectures, highlighting an area of the research that is
potentially of wider interest to asynchronous research community:
reconfigurable self-timed elements. These elements are
generalisations of standard self-timed element for synchronisation
(em the reconfigurable C-Muller gate ), and for control ( the
Select/Q-Merge pair). The reconfigurable C-Muller gate allows an
arbitrary synchronisation pattern to be defined between a set of
inputs. It has application beyond FPGAs to general routing
applications.
The Select/Q-Merge pair allows a wide variety of
control structures to be implemented, including variants of all the
control blocks used by Sutherland in his Micropipeline paper. An
important aspect of the Select/Q-Merge pair is their symmetry in
definition and usage, which matches well with the symmetry that
Sutherland highlights in the use of C-Muller gates in
Micropipelines.
A further generalisation, is to integrate reconfigurable elements
for synchronisation and control with delay elements to create a
general reconfigurable self-timed element called a Timing
Cell . Timing cells form the basis of the STACC self-timed FPGA
model. Each timing cell provides local register control (i.e. a
local clock) to a localised region of standard FPGA logic cells
(termed Data Cells ).
The STACC model has been used to design a self-timed version of the
Xilinx XC6200 FPGA. The self-timed XC6200 architecture is briefly
outlined in the presentation.
Availability
Run-time Parameterised Circuits for the Xilinx XC6200
Reference
R.E.Payne Run-time Parameterised Circuits for the
Xilinx XC6200. Proceedings of the
7th International Workshop on Field
Programmable Logic and Applications, September 1997
Abstract
Current design tools support parameterisation of circuits,
but the parameters are fixed at compile-time. In contrast, the
circuits discussed in this paper fix their parameters at run-time.
Run-time parameterised circuits can potentially out-perform custom
VLSI hardware by optimising the FPGA circuit for a specific instance
of a problem rather than for a general class of problem. This paper
discusses the design of run-time parameterised circuits, and
presents a study of run-time parameterised circuits for finite field
operations on the Xilinx XC6200. The paper includes a comparison
with implementation on a self-timed version of the XC6200
architecture, which illustrates the potential benefits of
self-timing for dynamically reconfigurable systems.
Availability
Asynchronous FPGA Architectures
Reference
R.E.Payne Asynchronous FPGA
Architectures . IEE
Proceedings on Computers and Digital Techniques, Special Issue on
Asynchronous Processors, September 1996.
Abstract
Field Programmable Gate Arrays (FPGAs) are of increasing importance
as processor support devices, and as computational devices in their
only right. Current synchronous FPGA architectures create problems for the
implementation of asynchronous circuits, due to their creation of
hazards, re-ordering of signals and lack of arbitration. This paper
examines how the first generation of asynchronous FPGA architectures
(MONTAGE, PGA-STC and STACC) tackle these problems.
Availability
Rob Payne
Last modified: Thu Sep 4 11:40:59 BST 1997